1. Field of the Invention
The present invention relates to integrated circuit technology. More particularly, the present invention relates to transmission gates and to gate boosting transmission gates.
2. Description of Related Art
As integrated circuits such as field-programmable gate array (FPGA) integrated circuits scale, the ability to overdrive n-channel pass gates is being severely compromised. Because of this limitation, it becomes advantageous to begin to use CMOS transmission gates even though they consume more area.
CMOS transmission gates can be speeded up by slightly overdriving the gates of the transistors used to form the transmission gates. Providing the positive voltage for overdriving the gates of the n-channel transistors is relatively simple, but providing the negative bias to overdrive the gates of the p-channel transistors is difficult. As a result, it has been proposed to only overdrive the gates of the n-channel transistors.
FIG. 1 is a schematic diagram that illustrates the problem solved by the present invention. FIG. 1 shows a typical transmission gate 10 including an n-channel transistor 12 and a p-channel transistor 14. Both n-channel transistor 12 and p-channel transistor 14 are low-threshold devices. While the term “low-threshold” is somewhat relative, depending on the process node and speed/power tradeoff made as engineering decisions, a low-threshold device may have a Vt (gate-to-source) of about 0.25V.
At the input node 16 of the transmission gate 10, one source/drain terminal of the n-channel transistor 12 is connected to one source/drain terminal of the p-channel transistor 14. At the output node 18 of the transmission gate 10, the other source/drain terminal of the n-channel transistor 12 is connected to the other source/drain terminal of the p-channel transistor 14.
The gates of the n-channel transistor 12 and the p-channel transistor 14 in the transmission gate 10 are driven from a latch 20 formed from a pair of inverters 22 and 24. The output of inverter 22 drives the input of inverter 24 and the output of inverter 24 drives the input of inverter 22. The circuit node comprising the output of inverter 22 and the input of inverter 24 is connected to the gate of the n-channel transistor 12 and the circuit node comprising the output of inverter 24 and the input of inverter 22 is connected to the gate of the p-channel transistor 14. The “high” state output of the latch is VDD, and the “low” state output of the latch is normally ground. The latch can be written to control the state of the transmission gate.
As shown in FIG. 1, in order to overdrive the input of n-channel transistor 12, a voltage of VDD+0.2 V is supplied to its gate. This voltage is relatively easy to provide at the outputs of the inverters 22 and 24 in the latch by slightly raising the power supply voltage to the inverters. In order to overdrive the input of p-channel transistor 14, a voltage of ground −0.2 V is supplied to its gate. This voltage is not easy to provide at the outputs of the inverters 22 and 24 since it requires providing a negative voltage supply on the integrated circuit. Providing a negative power supply voltage complicates the design of the integrated circuit.